module Learn8_2(clk,din,op); input clk,din; output op; ...
单项选择题module Learn8_2(clk,din,op); input clk,din; output op; reg[1:0] current_state,next_state; reg op; parameter S0=2’b00,S1=2’b01,S2=2’b10,S3=2’b11; always@( posedge clk) begin current_state <= next_state; end always@ (current_state or din) begin case ( current_state ) s0: if (din="=" 0) next_state="S0;" op="0;" else s1: s2: s3: default: endcase> A、该状态机是mealy型状态机
B、状态机的状态和输出仅在时钟上升沿改变
C、该状态机的输出只取决于当前的状态
D、该状态机的输出与下个状态也相关
